1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a fuse area structure in a semiconductor device and a method of forming the same.
2. Description of the Related Art
In general, a semiconductor device is realized by stacking various material layer patterns, and the uppermost layer thereof is covered with a passivation film. The passivation film is generally formed of a hard material such as silicon nitride. The passivation film absorbs mechanical, electrical, and chemical shock, thus protecting the semiconductor device.
In general, semiconductor devices such as semiconductor memory devices are subjected to a repair process to replace circuits that do not operate due to defects. The defective circuits are generally either replaced by redundant circuits or a trimming process is used to change the characteristics of some circuits such that they are suitable for a particular application. The repair process or the trimming process is performed by cutting part of a predetermined interconnection by irradiating with a laser. The interconnection cut by the irradiating laser is referred to as a fuseline. The cut part and area surrounding it are referred to as a fuse area.
FIG. 1 is a sectional view showing part of a memory cell and a fuse area of a conventional semiconductor device, in particular, a DRAM device employing a multi-layer metal interconnection structure.
The left side of FIG. 1 shows a cell array area, which includes a memory cell constituted of a transistor 14, 16, and 18 and a capacitor 30, 32, and 34, multi-layer metal interconnections 38 and 42, interlayer dielectric films 20, 26, 36, and 40, and a passivation film 44. Also, the right side of FIG. 1 shows the fuse area, which includes a fuse line, that is, a bitline 24, connected to the drain region 16 of the transistor by a bitline contact plug 22 and a fuse opening 50 obtained by etching interlayer dielectric films 36 and 40 and the passivation film 44 on the fuse line 24 by a predetermined width. The laser is irradiated through the fuse opening 50 to cut the fuse line 24 under the fuse opening 50. A field oxide 12 is formed on a substrate 10.
Here, each of the interlayer dielectric films 20, 26, 36, and 40 is described as a single-layer film. However, each can be a multiple-layer film obtained by stacking multiple layers. Also, a lower electrode contact plug 28 for electrically connecting a source region 18 of the transistor to the lower electrode 30 of the capacitor is located on a different plane to the plane on which the bitline 24 exists. That is, the lower electrode contact plug 28 does not contact the bitline 24. Here, it is described that the bitline 24 is used as the fuse line. However, the wordline 14 can be used as the fuse line. Another interconnection can be used as the fuse line in semiconductor devices other than memory devices. The above is also applied to the embodiments of the present invention, which will be described below.
The fuse area of the general semiconductor device having the structure as shown in FIG. 1 exhibits certain problems. The interlayer dielectric films 26, 36, and 40 exposed on the sidewall of the fuse opening 50 are formed of silicon oxide, in particular, boron phosphorous silicate glass (BPSG), phosphorous silicate glass (PSG), spin on glass (SOG), tetra ethyl ortho silicate (TEOS), and undoped silicate glass (USG) which have an excellent step coverage, in order to reduce a large step difference between a cell array area and a peripheral circuit area. However, the BPSG, the PSG, the SOG, and the TEOS, which contain a large amount of impurities, for example, greater than or equal to 5 weight % of boron or greater than or equal to 4 weight % of phosphorous, are vulnerable to moisture. The reliability of a semiconductor device in which a fuse area was formed is tested at the temperature of between 100 and 150xc2x0 C., under the humidity of between 80 and 100%, and under the pressure of between 1.5 and 3 atm. During this test, when moisture seeps into the interfaces between the interlayer dielectric films, which are vulnerable to moisture, as shown in FIG. 2, interfaces between metal interconnections 38 and 42 formed of tungsten or aluminum and the interlayer dielectric films 36 and 40 under the metal interconnections 38 and 42 in an adjacent peripheral circuit are peeled from each other as denoted by reference numeral 52. Accordingly, the electrical resistance of a metal contact increases and the reliability of the semiconductor device is severely deteriorated. It seems that because the energy level of the interface between the layers is lower than the energy level inside the respective layers that the moisture seeps into the interface between the interlayer dielectric films 26, 36, and 40 and the passivation film 44 and the interface between the interlayer dielectric films 36 and 40 and the metal interconnections 38 and 42.
In order to solve this problem as shown in FIG. 3, a fuse area in which a protection film 46 is formed of a material such as silicon nitride on the sidewall of the fuse opening 50 is provided in the invention disclosed in U.S. Pat. No. 5,879,966. However, in order to form the protection film 46, a process of depositing the silicon nitride film on the passivation film 44 and a photolithography process of exposing the interlayer dielectric film 26 on the bottom of the fuse opening 50 must be additionally performed.
The fuse opening 50 shown in FIGS. 1 and 3 is formed by allowing a predetermined thickness of the interlayer dielectric film 26 to remain on the fuse line 24 by sequentially etching the passivation film 44 and the interlayer dielectric films 40, 36, and 26 after forming the passivation film 44 of the uppermost layer. Here, the films to be etched are significantly thick. Accordingly, it takes a long time to etch the films. Also, it is difficult to accurately control the thickness of the interlayer dielectric film 26 left on the fuse line 24.
To solve the above problems, it is an object of the present invention to provide a fuse area structure in a semiconductor device capable of preventing moisture from seeping into the sidewall of a fuse opening.
It is another object of the present invention to provide a method of forming a fuse area of a semiconductor device by which it is possible to form a protection film on the sidewall of a fuse opening without additional processes.
It is still another object of the present invention to provide a method of forming a fuse area of a semiconductor device by which it is possible to reduce the time taken for etching the fuse opening without additional processes and to accurately control the thickness of an interlayer dielectric film left on a fuse line.
In accordance with the invention, there is provided a fuse area structure in a semiconductor device. The structure includes a fuse line and a first interlayer dielectric film formed on the fuse line and exposed by a fuse opening. A second interlayer dielectric film is formed on the first interlayer dielectric film, and the fuse opening is formed in the second interlayer dielectric film. A passivation film, which operates as a protection film for preventing moisture from seeping into the sidewall of the fuse opening, is integrally formed on the uppermost layer of the semiconductor device, on the second interlayer dielectric film, and the sidewall of the fuse opening.
The passivation film can be formed of a moisture-proof film, such as a silicon nitride film, a silicon oxide film or a compound film of silicon nitride and silicon oxide films.
In one embodiment, the first interlayer dielectric film is recessed from the surface of the first interlayer dielectric film in a portion exposed by the fuse opening. An interface between the first and second interlayer dielectric films is exposed on the sidewall of the fuse opening. The passivation film covers the exposed interface between the first and second interlayer dielectric films.
In one embodiment, the first interlayer dielectric film is recessed from the surface of the first interlayer dielectric film at a portion where the passivation film which covers the sidewall of the fuse opening ends.
According to another aspect of the present invention, there is provided a method of forming a fuse area. In the method of forming the fuse area, a fuse line is formed. A first interlayer dielectric film is formed on the fuse line. A fuse opening etching stop film is formed on the first interlayer dielectric film using a predetermined material layer of a semiconductor device to be formed, to be slightly wider than an area in which a fuse opening is to be formed. A second interlayer dielectric film is formed on the etching stop film. A contact hole for the semiconductor device is formed by etching the second interlayer dielectric film. A fuse opening for exposing the etching stop film is formed at the same time in the fuse area. An upper interconnection layer of the semiconductor device is formed by depositing a conductive material on the entire surface of each of the contact hole, the fuse opening and the second interlayer dielectric film and patterning the conductive material and removing the conductive material formed on the fuse opening at the same time. The first interlayer dielectric film is exposed by removing the etching stop film exposed to the fuse opening. The passivation film is formed on the entire surface of each of the upper interconnection layer, the fuse opening, and the second interlayer dielectric film. Finally, the first interlayer dielectric film is exposed by removing the passivation film deposited on the bottom of the fuse opening.
According to another aspect of the present invention, there is provided another method of forming a fuse area. In the method of forming the fuse area, a fuse line is formed. A first interlayer dielectric film is formed on the fuse line. A fuse opening etching stop film is formed on the first interlayer dielectric film using a predetermined material layer of a semiconductor device to be formed, to be slightly wider than an area in which a fuse opening is to be formed. A second interlayer dielectric film is formed on the etching stop film. A lower interconnection layer is formed on the second interlayer dielectric film in a region excluding the fuse area of the semiconductor device. A third interlayer dielectric film is formed on the lower interconnection layer. A contact hole which exposes the lower interconnection layer is formed by etching the third interlayer dielectric film. At the same time, a fuse opening which exposes the etching stop film is formed by sequentially etching the third and second interlayer dielectric films in the fuse area. A conductive material which will form an upper interconnection layer of the semiconductor device is formed on the entire surface of each of the contact hole, the fuse opening, and the third interlayer dielectric film. The conductive material layer is patterned, and the conductive material deposited on the fuse opening is removed. The first interlayer dielectric film is exposed by removing the etching stop film exposed to the fuse opening, and the passivation film is formed on the entire surface of each of the upper interconnection layer, the fuse opening, and the third interlayer dielectric film. The first interlayer dielectric film is exposed by removing the passivation film deposited on the bottom of the fuse opening.
The conductive material deposited on the fuse opening and the etching stop film under the conductive material can be successively removed using etching gas or etching solution having low selectivity.
The etching stop film can be removed after removing the passivation film on the bottom of the fuse opening.
The interface between the first interlayer dielectric film and the etching stop film is exposed on the sidewall of the fuse opening by slightly overetching the etching stop film of the fuse opening.